Research Engineer, Chip Design RL

About the Role

We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.

You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from.

Responsibilities

• Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
• Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape our roadmap.
• Deliver your work into research and production training runs.
• Collaborate with other researchers and engineers across and outside Anthropic.

Qualifications

• Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
• Fluency with industry EDA tools and processes.
• Experience taking chips from spec to silicon and taping out.
• Ability to balance research exploration with engineering implementation.
• Passion for AI's potential and commitment to developing safe and beneficial systems.
• Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience in a relevant field.

Nice to Have

• Experience with reinforcement learning, evaluations, or environments.
• Experience building tooling or automation around chip design flows.
• Background working on ML accelerators or high-performance compute hardware.
• Familiarity with high-level synthesis or architecture simulators.